The invention relates to an integrated circuit having a delay line arranged at a surface of a semiconductor body and comprising a series of signal storage capacitances, an input line for supplying signals and a read-out line for reading out the stored signals, a series of pairs of transistors, which are each associated with a signal storage capacitance and of which a transistor, the read-in transistor, constitutes a switch between the capacitance and the read-in line, while the other transistor, the read-out transistor, constitutes a switch between the capacitance and the read-out line, and further comprising a digital shift register having a number of outputs which are connected to control electrodes of the transistors.
Such an arrangement, which may be used inter alia for processing video signals, for example t.v. signals, is known from the article "Signalverarbeitung mit analogen Speichern in der Fernsehtechnik" of G. Brand, published in "Fernish- und Kinotechnik", Vol. 30, No. 3 (1976), pp. 81-85. FIG. 5b of this publication shows diagrammatically a delay line, in which the storage capacitances together with the associated pairs of transistors and the shift register are consecutively arranged in a linear configuration. The signals to be stored are supplied via the input line. By means of the shift register and the read-in transistors controlled by the shift register, the signal storage capacitances are successively connected to the input line. When the signal has been stored, the connection between the input line and the capacitances is interrupted again, as a result of which the signal value supplied at the input line remains present at the capacitance for a desired delay time. When reading out, the read-out transistors are successively rendered conducting by the shift register, as a result of which the stored signals appear successively at the read-out line and can be read out via an amplifier.
The value of the (voltage) signal at the read-out line is determined in analogy with dynamic memories by the ratio between the signal storage capacitance and the parasitic capacitance of the read-out line. Because of the disturbance margins to be taken into account, it is desirable that the difference between the highest value and the lowest value of the signals be as great as possible. For this reason, the parasitic capacitance of the read-out line is kept as small as possible.